1. Field of the Invention
The present invention relates to a compound semiconductor device and a method of manufacturing the same and, more particularly, an FET manufacturing method utilizing a field effect transistor (referred simply to as an "FET" hereinafter) and an ion implantation process.
2. Description of the Prior Art
As typical devices as a transistor employing compound semiconductor, there are a GaAs MES FET (Metal Semiconductor FET), a HEMT (High Electron Mobility Transistor), etc. The GaAs MES FET has such features that a high frequency operation can be achieved with low noise, a high speed switching operation can be achieved, etc. Thus, the GaAs MES FET is suitable for various applications, e.g., a high frequency/high output amplifier, a high frequency/low noise amplifier, a high speed change-over switch, etc. At present, the GaAs MES FET has been broadly used as a gate array, an amplifier IC in the mobile communication, a high speed optical communication IC, etc. Also, with the progress of information communication technology in recent years, a higher operational speed of the device is now requested.
The GaAs semi-insulating substrate is employed in the GaAs MES FET, and GaAs is a compound semiconductor consisting of a group III element and a group V element. A device using such compound semiconductor is called a compound semiconductor device. Since Gals has a high electron mobility and a high saturation drift velocity, it is fitted for a high speed/high frequency device. More particularly, the electron mobility in a pure GaAs is higher about five times than silicon (Si), and a peak velocity of the saturation drift velocity of the pure GaAs is higher about twice than the saturation velocity of Si. In addition, since the pure GaAs has the high mobility, an electric field required for the peak velocity is small rather than Si. Further, since GaAs can be formed as a crystal with higher resistance rather than Si, such GaAs is called a semi-insulating crystal. Therefore, if a single device or an integrated circuit is fabricated by using a semi-insulating substrate, a parasitic capacitance can be reduced generally and device isolation can be facilitated.
As with GaAs MES FET manufacturing method, the self-alignment FET employs the gate electrode made of WSi, or the like, whose gate characteristic is not deteriorated even when the high temperature annealing process is applied to the gate electrode, as a mask for n.sup.+ ion-implantation. Such self-alignment FET has a very small source resistance Rs because an n.sup.+ layer is formed in close vicinity of the gate, and the manufacturing steps are relatively simple because such self-alignment FET is formed as a simple planar structure without a recess structure, so that such self-alignment FET has been broadly used.
An operation speed of the MES FET is decided by a cut-off frequency f.sub.T which is in inverse proportion to the gate length Lg. Therefore, in order to accelerate the operation speed, it is an effective means to reduce the gate length Lg. However, in reducing the gate length Lg, sometimes a phenomenon which is called a short channel effect such as increase in a drain conductance or increase in a well up current occurs to thus deteriorate device characteristics.
Following points can be pointed out as causes of the short channel effect.
(1) The channel thickness tch must be reduced to mate with reduction of the gate length Lg and also impurity concentration of the channel region must be increased such that an aspect ratio of gate length/channel thickness (Lg/tch) is not so reduced. However, this aspect ratio is not set in the appropriate range. The gate length is a length of the gate electrode in a direction from a source region to a drain source region.
(2) The potential of a depletion layer immediately below the gate electrode extends downward with the reduction of the gate length Lg, so that thermionic emission into the semi-insulating substrate becomes prominent.
(3) The current which flows between opposed n.sup.+ regions, i.e., a highly doped layer below the source electrode and a highly doped layer below the drain electrode, via the semi-insulating substrate is increased.
Among these causes of the short channel, it is evident that the cause (1), i.e., the aspect ratio (Lg/tch) is not set in the appropriate range, can be improved by executing the ion-implantation into the n-type channel region at the low energy and the high dosage.
In order to prevent the thermionic emission into the semi-insulating substrate set forth in the cause (2) and the increase in the current flowing between the opposed n.sup.+ regions set forth in the cause (3), the structure which is known as the "buried p type region" is effective. In the buried p type region structure, the buried p type region is formed in the semi-insulating substrate side which contacts the channel region and the n.sup.+ region to form pn junction and thus depletion layers are formed on interfaces between the channel region and the n.sup.+ region and the semi-insulating substrate to prevent the leakage current.
FIGS. 1A to 1C are views showing the typical buried p type region structure in the FET as the compound semiconductor device in the prior art. FIG. 1A is a sectional view showing the compound semiconductor device employing the buried p type region structure, FIG. 1B is a plan view (top view) showing the buried p type region structure in FIG. 1A, and FIG. 1C is a sectional view showing an issue of the compound semiconductor device in the prior art, i.e., leakage current paths between elements. In the compound semiconductor device employing the buried p region structure shown in FIGS. 1A to 1C, a p-type impurity region 20 is formed on a surface of a semi-insulating substrate 10 by ion implantation using photoresist (not shown) as a mask, and then an n-type active region (channel region) 40 is formed by another ion implantation using the same photoresist (not shown) as a mask. Then, a gate electrode 50 is formed on the channel region 40, then openings (not shown) on the semi-insulating substrate 1 are formed in an SiO.sub.2 film (not shown) and a photoresist film (not shown) on the basis of the gate electrode 50 as an alignment mark, and then a high concentration n-type impurity region (source region) 60-1 and a high concentration n-type impurity region (drain region) 60-2 are formed by ion implantation on both sides of the gate electrode 50 via the openings in a self-alignment manner. These regions are then activated by the annealing process, and then a source electrode 80-1 and a drain electrode 80-2 are formed.
Next, conception of the buried p structure will be explained in brief with reference to FIGS. 2A to 2C hereunder. As shown in FIG. 2A, the buried p type structure has a p-type impurity region 20 which is buried below the n-type active region 40, the high concentration n-type impurity region 60-1 and the high concentration n-type impurity region 60-2. FIG. 2B is a view showing an ion implantation energy in the buried p structure at a depth x from the surface of the substrate 1 which corresponds to positions of the n-type active region 40 and the p-type impurity region 20 in FIG. 2A. In FIG. 2B, the n-type and p-type impurities are overlapped on a boundary portion between the n-type active region 40 and the p-type impurity region 20 (shaded area). Carriers are canceled in this overlapping area and thus, as shown in FIG. 2C, n-type implantation carriers remains sharply in the n-type active region 40, whereby the thin channel can be formed. The pn junction below the thin channel is formed as a depletion region.
However, it has already been found that, when the device shown in FIGS. 1A to 1C is manufactured actually by way of trial, the leakage current generated by the n-type conduction (electron conduction) 11 between fringes of the high concentration n-type impurity regions 60-1, 60-2, as shown in FIG. 1C, is increased, and thus both reduction in the pinch-off characteristic between the source-drain regions and degradation of the isolation characteristic between neighboring devices are caused.
In order to overcome the above problems, the proposal has been made wherein the ion implantation regions constituting the high concentration n-type impurity regions 60-1, 60-2 should not be formed identically in the width direction to be aligned with the p-type impurity region 20, but the high concentration n-type impurity regions 60-1, 60-2 should be formed to be surrounded by a p-type impurity region 21, as shown in FIGS. 3A and 3B. In other words, the p-type impurity region 21 is positioned on the outside of the high concentration n-type impurity regions 60-1, 60-2 by about 0.5 .mu.m by expanding outward from respective side end portions of the high concentration n-type impurity regions 60-1, 60-2, so that the p-type impurity region 21 can be formed on the outside of the high concentration n-type impurity regions 60-1, 60-2.
In such buried p structure wherein the p-type impurity region 21 is extended from the n-type active region, it has been found that, in the FET having the gate length Lg of more than about 0.5 .mu.m, the short channel effect can be sufficiently suppressed and thus good device characteristics can be achieved.
However, in the FET having the shorter gate length Lg, e.g., Lg.ltoreq.0.35 .mu.m, the channel region must be formed under considerably low energy/high dosage condition. Thus, the optimum p-type impurity region 21 must also be formed inevitably under the low energy/high dosage condition to mate with such channel region.
In other words, commonly it is said that the short channel effect becomes prominent when the gate length/channel thickness (Lg/tch) value is less than about 4.0 to 5.0. In order to avoid the short channel effect, the channel thickness (depth) tch must be thinned in correspondence to reduction in the gate length Lg. However, when the channel thickness tch is thinned, dosage of a channel region 41 must be increased inevitably in order to ensure a predetermined current flowing through the channel, i.e., to keep (channel thickness tch).times.(dosage)=constant.
In this manner, when the channel region 41 is highly dosed, the p-type impurity region 21 formed below the channel region 41 must also be highly dosed correspondingly. More particularly, since the channel region 41 is formed shallow (thin) and is highly dosed, the p-type impurity region 21 is also positioned at a shallow location and must be dosed highly enough to compensate the highly dosed n-type active region 41. Accordingly, the p-type impurity region 21 positioned at the periphery of the FET also becomes the highly dosed region.
As a result, as shown in FIG. 4A which is a sectional view taken along a line I--I in FIG. 3B, it has been experimentally confirmed that, in the Schottky junction between a metal and a p-type layer, i.e., between a gate electrode 50 and the high concentration p-type impurity region 21, a hole conduction current flowing from the high concentration p-type impurity region 21 to the gate electrode 50 becomes prominent at a portion other than the channel region of the FET. Therefore, the Schottky barrier junction cannot be kept and thus sometimes the pinch-off characteristic of the FET is damaged.
In addition, as shown in FIG. 4B which shows two neighboring devices, a distance between the neighboring devices is reduced since the p-type impurity region 21 is extended, and sometimes p-type conduction (hole conduction) 12 is caused between the high concentration p-type impurity regions 21 of the neighboring devices via the substrate 1 since the p-type impurity region 21 is highly doped. In order to suppress the p-type conduction 12 between the neighboring p-type impurity regions 21, it is needed to extend physically the device distance, which goes against the miniaturization of the device.
Like the above, the problem such that the pinch-off characteristic of the device is damaged or the highly doped p-type impurity regions 21 is exposed from the side surface if the channel is optimized. Conversely, the appropriate channel region cannot be kept if the device is designed to clear up such problem.
Typically such problems become issues of the FET of the short gate length. However, essentially such problems are not limited to the FET of the short gate length. More particularly, in the FET having the gate length Lg of about 1.0 .mu.m, if the high concentration and thin active layer and the buried p structure are formed, the problems described in connection with FIGS. 4A and 4B also occur.